Calibration of Microprocessor Performance Models

This paper outlines a method for calibrating a superscalar processor performance model. It is adapted from and integrates well with the existing tools and method used in industry for hardware functional validation. The goal of this study is to identify the risks of developing a performance model with inspection-based validation. It is shown that such a model can exhibit major latency and behavioral discrepancies against the actual hardware. A performance model constructed for the PowerPC 604 processor is shown to model the latency of only 50% of all instructions, and the pipeline flow behavior of only 30% of all instructions. Using our calibration method it is possible to very quickly identify enough model errors and improve the above percentages to 96% and 75% respectively. Three types of errors are documented and discussed: modeling errors, specification errors, and abstraction errors. Based on the calibration approach used in this study, we propose a systematic method for ensuring the accuracy of performance models.